Cache-conscious offline real-time task scheduling for multi-core processors

Viet Anh Anh Nguyen (1) , Damien Hardy (1) , Isabelle Puaut (1)

1 PACAP - Pushing Architecture and Compilation for Application Performance

Most schedulability analysis techniques for multi-core architectures assume a single Worst-Case Execution Time (WCET) per task, which is valid in all execution conditions. This assumption is too pessimistic for parallel applications running on multi-core architectures with local instruction or data caches, for which the WCET of a task depends on the cache contents at the beginning of its execution, itself depending on the task that was executed before the task under study. In this paper, we propose two scheduling techniques for multi-core architectures equipped with local instruction and data caches. The two techniques schedule a parallel application modeled as a task graph, and generate a static partitioned non-preemptive schedule. We propose an optimal method, using an Integer Linear Programming (ILP) formulation, as well as a heuristic method based on list scheduling. Experimental results show that by taking into account the effect of private caches on tasks' WCETs, the length of generated schedules is significantly reduced as compared to schedules generated by cache-unaware scheduling methods. The observed schedule length reduction on streaming applications is 11% on average for the optimal method and 9% on average for the heuristic method.

Mots clés: Real-time scheduling; Cache-conscious scheduling; Many-core architectures; ILP; Static list scheduling

Domaines: Architectures Matérielles [cs.AR]; Calcul parallèle, distribué et partagé [cs.DC]; Systèmes embarqués; Performance et fiabilité [cs.PF]

Viet Anh Anh Nguyen, Damien Hardy, Isabelle Puaut. Cache-conscious offline real-time task scheduling for multi-core processors. 29th Euromicro Conference on Real-Time Systems (ECRTS17), Jun 2017, Dubrovnik, Croatia. ⟨10.4230/LIPIcs.ECRTS.2017.14⟩. ⟨hal-01590421⟩